Code

COMP1001

Year

1

Prerequisites

none

Term

1

Taught By

Steve Hailes (50%)
Kevin Bryson (50%)

Aims

To show how information is represented in a computer. To explain how computers execute instructions to 'process' data. To explain the structure and interconnection of computers and the reasons for this. To show how programs are mapped on to the architecture. To demonstrate the basics of I/O, the role of the interface, and the use of polling, interrupts and DMA. To cover the architectural requirements to provide for secure multi-user, multi-processing systems. Performance issues must pervade the course material, but there is a need to deal with specific architectural features that enhance performance: cache memory, pipelining, superscalar architectures. To establish the role of the operating system in managing resources and providing for multiprocessing. To educate students to understand the design and performance of the most common computer systems from micro-controllers (the commonest) to workstations (the most well-known).

Learning Outcomes

Students will understand the basic principles behind the design of modern computer systems, and will be able to apply them to novel designs that they may come across in the future - abstraction (from instruction set to assembler programming, from processor and memory and bus hardware up to operating systems and compilers) is a key understanding outcome.

Part One (problem-based learning, continuous assessment) - taught by Steve Hailes

Material covered in part I: 1) Introduction. 2) Logic gates.  3) Combinatorial composition of gates: rules of logic, SOP and POS forms, Karnaugh maps, multiplexers. 4) Sequential circuits; SR latches, D latches, D flip flops. 5) Finite state machines 6) Single cycle processor design, ALU, Counters, Shift registers, MIPS instructions, Memory, Datapath design for different instructions, Memory mapped i/o.

In the first week of term, the students are given three lectures; in subsequent weeks a single lecture per week. The remainder of the work is practical in nature; each student may attend three hours of supervised labs per week, but is expected to undertake  extra work in their own time. We make use of the spartan-3E FPGA development board and Xilinx software to create the individual subcomponents of a single cycle computer (as schematics rather than in HDL) - both directly and as related exercises - which are then developed and integrated to produce a working system. The course makes use both of simulation and actual hardware; the Xilinx software environment is provided on a virtual machine that means students are presented with the same development environment outside the labs as inside the labs.

The course is designed around a problem-based learning ethos. After an initial hands-on period, the students are not provided with sufficient information in the lectures to complete the lab tasks, though the difficulty of obtaining it is tapered. In the beginning students are directed to extra reading, but later tasks require them simply to discover things for themselves. The result is that course is very intensive.
Students work as pairs and are assessed as pairs; the pairs are chosen by the course organiser. The work is practical, and the marking is binary, per exercise, based on the ability of students to demonstrate a working solution, to explain its operation, and to answer questions about it. Both students in a pair are required to contribute to each assessment.

Part II (Lectures and coursework) - taught by Kevin Bryson

Computer Architecture: Internal structure of processor/CPU – registers, PC, ALU, CU, etc. Bus architecture and processor interaction with memory and peripherals, Memory hierarchy in terms of cache memory, main memory, secondary storage, Memory organisation into bytes and words; big-endian and little-endian organization.

Data Representation: Representation of strings,Binary and hex integer representations and conversions,Signed and unsigned formats; 2's complement,Computer integer arithmetic, Fixed-point arithmetic, IEEE floating point representation and arithmetic.
Machine Instructions and Assembly Code: Fetch-Execute cycle,Encoding and decoding of MIPS machine instructions,The MIPS CPU instruction set syntax and semantics, Addressing modes, MIPS assembly language programming, Register usage conventions, Use of stack and stack-frame for supporting function calling with parameters, Operating system calls and I/O operations.

Lecture presentations, problem classes, lab sessions and tutorial sessions. 

100% coursework. Two written courseworks and lab-based project work.

To pass this course, students must:

• Obtain an overall pass mark of 40%

Available on Moodle