From Wetware to Hardware: Reverse Engineering Using Probabilistic RAMs

T G Clarkson, D Gorse and J G Taylor

Journal of Intelligent Systems, 2, 11-30, 1992

A model of neural processing is described which is able to incorporate a great deal of neurophysiological detail (synaptice noise, synapse-synapse interactions, cell surface geometry, temporal features) and which is capable of hardware realisation as a 'probabilistic random access memory' (pRAM). The model can operate either in a binary mode or can integrate the effects of incoming spike trains to perform a real-to-binary mapping ('integrating pRAM' or i-pRAM). pRAMs can be trained using a variety of techniques, in particular reinforcement training, which has the advantage of beign wholly realisable in hardware as well as having greater biological plausibility than supervised techniques.