COMP0008 Computer Architecture and Concurrency

This database contains the 2018-19 versions of syllabuses.

Note: Whilst every effort is made to keep the syllabus and assessment records correct, the precise details must be checked with the lecturer(s).

Academic session



Computer Architecture and Concurrency



Module delivery

1819/A5U/T1/COMP0008 Undergraduate

Related deliveries


Prior deliveries




FHEQ Level


FHEQ credits



Term 1

Module leader

Bryson, Kevin


Bryson, Kevin

Module administrator

Ball, Louisa


To provide a working knowledge of the hardware and architecture of a modern computer system, particularly focusing on concurrency aspects and those that have an impact on writing multithreaded software. Students will gain a fundamental understanding of the concurrency abstraction and how it impact both hardware and software design. We will look at concurrency aspects of hardware: how race conditions in hardware can cause logic glitches; using parallelism to build efficient adder units and CPU pipeline designs. We will also look at hardware aspects that directly impact multithreaded software such as the memory hierarchy, cache coherence/consistency and hardware multithreading. We will learn how to design correct multithreaded Java software based on a solid theoretical understanding of concurrency principles and the Java Memory Model. The module will cover an understanding of concurrency from low-level aspects (such as spin locks implemented with MIPS hardware instructions) to high-level design patterns used within the Java concurrency package.

Learning outcomes

On successful completion of the module, a student will be able to:

  1. use the concurrency abstraction to reason about concurrent systems (both hardware and software)
  2. understand combinatorial and sequential digital logic circuits and be able to reason about them
  3. write and understand MIPS32 assembly language programs
  4. understand how high-level languages are translated to assembly language and subsequently machine code that drives the MIPS32 processor
  5. understand the internal structure of processors and different forms of parallelism employed
  6. develop an appreciation of how modern computers handle memory and input/output including key concurrency aspects such as cache coherence, memory consistency/visibility and interrupt-driven thread switching
  7. understand how operating systems schedule application level threads onto the hardware resources
  8. understand how synchronization mechanisms in high-level languages are implemented in terms of more primitive hardware concurrency instructions
  9. understand and resolve safety aspects of multithreaded Java including interference and visibility issues
  10. understand the monitor design pattern and how to employ it to write safe and efficient multithreaded Java code using both the traditional concurrency mechanisms and the new Java concurrency package classes
  11. understand and correctly use the thread-safe data structures and thread control mechanisms within the Java concurrency package

Availability and prerequisites

This module delivery is available for selection on the below-listed programmes. The relevant programme structure will specify whether the module is core, optional, or elective.

In order to be eligible to select this module as optional or elective, where available, students must meet all prerequisite conditions to the satisfaction of the module leader. Places for students taking the module as optional or elective are limited and will be allocated according to the department’s module selection policy.

Programmes on which available:

  • BSc Computer Science (Year 2)
  • MEng Computer Science (International Programme) (Year 2)
  • MEng Computer Science (Year 2)
  • MEng Mathematical Computation (International Programme) (Year 2)
  • MEng Mathematical Computation (Year 2)


In order to be eligible to select this module, students need to:

  • understand basic propositional logic (Boolean algebra, normal forms, Karnaugh maps, etc.);
  • basic computer arithmetic (binary/hex manipulation, fixed-size arithmetic, 2s- and 16s-complementary forms, etc.);
  • and also have strong Java programming skills.


  • Top-down high level overview of a computer: the main components making up a computer and how they interact.
  • The concurrency abstraction applied to hardware and software.
  • Fundamentals of hardware: basic electronics, logic gates and logic circuits.
  • Combinatorial logic: building adders, subtractors and arithmetic logic units (ALUs).
  • Sequential logic: building latches, flip-flops and CPU registers.
  • MIPS assembly language and machine code.
  • Translation of high-level languages into MIPS machine code.
  • Internal structure of a MIPS processor: the control unit (CU) and datapath.
  • Parallelism within the CPU.
  • Key aspects of how operating systems handle application-level threads.
  • Memory hierarchy, cache structure and cache coherence mechanisms.
  • Creating and managing Java threads.
  • Java traditional synchronization mechanisms (and how they relate to low-level hardware instructions)
  • Monitor design patterns and conditional variables.
  • Java concurrency package: thread control classes and thread-safe data structures.
  • Understanding and reasoning with the Java Memory Model (JMM) specification.
  • Reasoning about the correctness of concurrent programs: safety, variable visibility, liveness and deadlocks.

An indicative reading list is available via


The module is delivered through a combination of lectures, electronic coursework and programming exercises.


This module delivery is assessed as below:



Weight (%)



Written examination (2hrs)




Coursework 1




Coursework 2




Coursework 3



In order to pass this Module Delivery, students must:

  • achieve an overall weighted Module mark of at least 40.00%;

AND, when taken as part of BSc Computer Science; MEng Computer Science, and MEng Mathematical Computation:

  • achieve a mark of at least 30.00% in any Components of assessment weighed ≥ 30% of the module.

Where a Component comprises multiple Assessment Tasks, the minimum mark applies to the overall component.